High speed ratioed CMOS logic structures for a pulsed input envi

Details High speed ratioed CMOS logic structures for a pulsed input envi High speed ratioed CMOS logic structures for a pulsed input envi

1997-12-29

1999-08-24

Tokar, Michael

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 86, 326 98, H03K 19094, H03K 1920

Patent

active

059429178

ABSTRACT:
A logic structure adapted to receive pulsed active input signals produces a logical output with a very small inherent switching delay. Pull-down transistors and complementary pull-up transistors are ratioed such that the default logical output level remains close to nominal even when the logic structure sinks or sources a DC current. When the pulsed input signals are inactive, no DC current path is enabled.

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patent: 5592103 (1997-01-01), Sutherland
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