Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1996-10-11
2001-04-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000
Reexamination Certificate
active
06218856
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to programmable logic, and in particular to a high speed programmable logic device architecture, employing active driver circuits in the interconnection array.
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control to customize the logic functions the circuit will perform. The logic functions previously performed by small, medium, and large scale integration integrated circuits are now capable of being performed by programmable logic devices. PLDs now have a capacity on the order of 50,000 gates per integrated circuit. When a typical programmable logic device is supplied by an integrated circuit manufacturer, it is not yet capable of performing any specific function. The user, however, in conjunction with software, also typically supplied by the programmable logic device manufacturer, can program the PLD to perform the specific function or functions required by the user's application. The PLD then can function in a larger system designed by the user, just as though dedicated logic chips were employed. This functionality allows the user to debug the system logic without committing the time or expense of custom chips or gate arrays. It also allows small production runs, and the customization of hardware to suit a very specific application. In some PLD's the logic can be changed “on-the-fly” enabling the PLD to perform one function at one time during system operation, and another function at a later time.
A typical PLD consists of an array of identical logic cells that can be individually programmed, and which can be arbitrarily interconnected to each other to provide internal input and output signals, thus permitting the performance of implemented in the PLD by setting the states of programmable elements such as memory cells.
One type of programmable logic, known as programmable logic arrays (PLA) is a combinatoral two-level AND/OR integrated circuit which can be programmed to perform sum-of-products logic. Such devices typically consist of a series of AND gates having input terminals which can be programmably connected to chip input signals, and a series of OR gates which may be programmably connected to receive the output signals from the AND gates.
Another type of programmable logic device is known as programmable array logic (PAL). PALs use a fixed OR array and bidirectional input/output pins. A disadvantage of both PALs and PLAs is the lack of density with which they may be programmed. In other words, although the array is capable of performing many logic functions, utilization of the array is not as complete as desirable. Furthermore the size of the array increases faster than its programming capability.
A response to this problem has been the provision of “macrocells” or logic blocks in programmable logic devices. A macrocell or logic block is a small grouping of logic capable of performing many different functions, and being selectively interconnectable to other macrocells or logic blocks. This allows the logic in the programmable logic device to assume a more granular structure in which pieces of the logic communicate with other pieces, to provide an overall more efficient utilization of the integrated circuit. Herein I use the phrase “programmable logic device” to refer collectively to programmable array logic, programmable logic arrays, field programmable gate arrays, and other types of programmable logic devices.
A significant disadvantage of all programmable logic devices presently available is their relatively slow speed. In all of the programmable logic devices described above, the connections within the AND and OR arrays, as well as to and from the macrocells, are made with erasable programmable read only memory cells, electrically erasable read only memory cells, static random access memory cells, fuses, or antifuses, or the like. In each of these cases, the interconnection approach is passive. That is, the state of a memory cell or fusible connection is itself used to control some other apparatus which makes or breaks a connection between two nodes.
All of these connections are passive in the sense that the signals presented to the connection simply pass through the connection (or do not pass if the connection is open). As a result, the overall speed of the programmable logic device is limited for reasons discussed below. Even the fastest prior art large field programmable gate arrays presently available operate at 50 mhz or slower. Some small transistor-transistor logic (TTL) devices can operate at over 100 megahertz. No one is presently manufacturing large fast arrays.
One of the primary reasons for the relatively slow operating speed of prior art programmable logic devices is the resistance present in the interconnection system. The interconnection system is the programmable “wiring” by which the logic signals are propagated across the integrated circuit chip. This propagation speed is limited by the series resistance of the transfer gates employed, whether formed as EPROM cells, SRAM cells, antifuses, or otherwise. As a result, manufacturers of prior art programmable logic devices have been forced to chose between resistance and capacitance in the technology selection for their transfer gates.
As described above, in a typical prior art programmable logic device, the logic is implemented in logic blocks which communicate with each other. Such logic blocks when coupled with transfer gates have an effective drive resistance on the order of 1000 ohms per connection plus the resistance of the driver circuit. In antifuse technology, for example, as implemented by Actel Corporation, the effective drive resistance is on the order of 50 to 500 ohms per connection plus the resistance of the driver circuit. As will be described, in the technology of our system, the effective drive resistance is simply the resistance of the driver circuit.
SUMMARY OF THE INVENTION
We have developed an architecture for programmable logic devices which is capable of operating at substantially greater speeds than prior art programmable logic devices. In a preferred embodiment of our system, speeds of up to 500 mHz are achievable using the programmable logic techniques of our system and presently available silicon semiconductor technology.
In one implementation of our invention, a routing structure is provided for a programmable logic circuit which includes logic cells in which logic functions are performed. The routing structure includes a set of input lines generally extending in a first direction for supplying signals to be processed by the logic cells, and a set of output lines extending in a different direction for receiving signals which have been processed by the logic cells. Where the input and output lines cross, junction regions are established which include controllable active driver circuits which are capable of programmably providing, or not providing, connections between selected ones of the set of output lines and selected ones of the set of input lines to enable signals present on the output lines to be placed on desired ones of the input lines. Each of the controllable driver circuits is a buffer circuit capable of being placed in at least an active state in which the driver circuit replicates a signal supplied to it, or in a passive state in which it presents a high impedance between its input and output. Typically, the controllable driver circuits enable each output line in the set to be connected to any desired ones in the set of input lines.
In another embodiment, our system includes a similar structure to that described immediately above, but in addition provides a set of controllable driver circuits to selectively interconnect desired ones of the input lines and the output lines to the logic cells. In this manner, input signals present on the input lines can be supplied to the appropriate nodes of the logic cell, and output signals from the logic cells can be supplied to other desired logic cells or other circuitry.
In conjunction
Paik Steven S.
Tokar Michael
Xilinx , Inc.
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