High speed reduced area multiplexer

Details High speed reduced area multiplexer High speed reduced area multiplexer

1995-09-27

1997-01-28

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326106, 327408, H03K 19094, H03K 19084

Patent

active

055981143

ABSTRACT:
A multiplexer that comprises a first input buffer and a first pass gate coupled in series between a first data input and a common node and a second input buffer and a second pass gate coupled in series between a second data input and the common node. A biasing circuit is coupled to the common node and a supply voltage to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node. An output buffer is coupled to the common node for outputting an output signal to a data output in response to a voltage of the common node.

REFERENCES:
patent: 4620117 (1986-10-01), Fang
patent: 4985647 (1991-01-01), Kawada
patent: 4985703 (1991-01-01), Kaneyama
patent: 5162666 (1992-11-01), Tran
patent: 5233233 (1993-08-01), Inoue et al.

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