High speed pipeline method and apparatus

Electronic digital logic circuitry – Multifunctional or programmable – Array

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Details

395800, 395377, 326 17, G06F 900

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active

057322333

ABSTRACT:
A data processing apparatus has a number of data processors connected in a series by data lines so that data signals are processed in a preceding processor and communicated to a succeeding processor in the series. The apparatus has a number of control elements, where a control element has first and second inputs receiving processor status signals and an output sending a signal to enable processing. The control element output assumes a certain output state only if both inputs assume the state. The output, having assumed the state, holds the state, despite one of the inputs not holding the state, only if a certain one of the inputs does hold the state.

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Franklin et al., "Clocked and Asynchronous Instruction Pipelines", Microarchitecture, 1993 International Symposium, IEEE, Dec. 1993, pp. 177-184.
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Karthik et al., "Interlock Schemes for Micropipelines: Application to a Self-Timed Rebound Sorter", Computer Design -ICCD'91, 1991 International Conference, IEEE, Oct. 1991, pp. 393-396.
I.E. Sutherland, Micropipelines, Communications of the ACM, Jun. 1989, vol. 32, No. 6.

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