Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate
2001-04-09
2002-10-01
Le, Thien M. (Department: 2876)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
C326S040000, C326S106000, C326S113000, C365S230060
Reexamination Certificate
active
06459303
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of programmable integrated circuits and in particular, to decoder circuitry for an embedded memory of a programmable logic device.
Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modern programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Many programmable logic integrated circuits also included embedded user-programmable memory or RAM.
There is a continuing desire to provide greater functionality in a programmable logic integrated circuit, but at the same time, provide greater performance. One of the critical speed paths of the programmable logic integrated circuit is the read and write paths of the memory. It is desirable that reading and writing of the memory is a high-speed path. A memory address is decoded to access the appropriate location in the embedded memory. The address decoding delay is part of the read and write delay in accessing the memory.
Therefore, there is a need to provide high performance address decoding techniques and circuitry in order to improve the performance of the integrated circuit.
SUMMARY OF THE INVENTION
The invention provides a high-performance address decoder circuitry techniques. The address decoder is programmable to allow addressing of the memory in different data widths and depths, which is an especially desirable feature for an embedded memory of a programmable logic integrated circuit. The circuitry can be used as column address decoder or row address decoder, or both. In a dual port memory version of the memory, there may be two instances of each of the decoders, one for writing and one for reading.
In an embodiment, the column decoder circuitry of the invention includes two stages. The first stage is an address predecoder. The first stage address predecoder outputs an intermediate decoded address that is input to second stage. The second stage is a decoding circuit and decoder driver. The second stage provides the decoded address bits that are connected to the memory being addressed. A multiplexer control signal generation circuit generates control bits that are input to the first stage. These control bits are based on a number of programmable configuration bits and control the data width selection of the memory. The programmable configuration bits are user programmable.
Memories are used in many types of integrated circuits, including microprocessors, controllers, ASICs, programmable logic devices (PLDs), FPGAs, DRAMs, SRAMs, EPROMs, and many others. More information on PLDs may be found in the 1998
Altera Data Book,
which is incorporated by reference. Some integrated circuits, such as PLDs, may include memory blocks that have a programmable data width feature.
This means the dimensions of the array of memory cells may be programmably varied. For example a memory block may be arranged as 2K×16, 2K×8, 8K×4, 16K×2, and 32K×1, as well as many other configurations. For a 2K memory block, some configurations include 128×16, 256×8, 512×4, 1024×2, and 2048×1. For a 4K memory block, some configurations include 128×32, 256×16, 512×8, 1024×4, 2048×2, and 4096×1. A circuit of the present invention is a high performance column address decoder. This column address decoder may, for example, be used in Altera's FLEX® 10K, APEX™ 20K, or APEX™ 20KE series of products or APEX20K400 product to address the EABs or ESBs.
In an embodiment, the invention is an integrated circuit including a first stage decoding circuit having a plurality of address bit inputs and generating a plurality of intermediate address bits. A second stage decoding circuit is connected to the intermediate address bits and generates a plurality of decoded address bits. A multiplexer control signal generation circuit generates a control signal for the first stage decoding circuit.
In another embodiment, the invention is a programmable logic integrated circuit including an embedded memory block, where a data width and depth of the embedded memory block are programmably selectable. A column decoder for the embedded memory includes a first stage decoding circuit. The first stage decoding circuit includes a first address input connected to a first inverter, where an output of the first inverter is connected to a first input of a first multiplexer and a second inverter. An output of the second inverter is connected to a second input of the first multiplexer and a second intermediate decoded address line. And an output of the first multiplexer is coupled to a first intermediate decoded address line. A second stage decoding circuit includes a plurality of logic gates having inputs connected to the first and second intermediate decoded address lines, where the second stage decoding circuit generates a first decoded address list, connected to the embedded memory block.
FIG. 6
shows a block diagram of an interpretation of decoder circuitry of the present invention. Address inputs are connected to a first stage decoding circuit. A control logic block generates multiplexer control signals from data width selection bits. The multiplexer control signals are input to the first stage decoding circuit. The first stage decoding circuit outputs an intermediate decoded address, which is input to a second stage decoding circuit and decoder driver. The second stage decoding circuit generates the decoded address.
The decoding circuitry of the present invention provides high performance, and is faster than other decoding techniques. The circuitry is about 24 percent faster than other decoding circuitry in ×1mode, and about 65 percent faster in the ×16 mode. The present decoding circuitry reduces performance skew among the different data widths. The circuitry also has fewer transistors and fewer wire connections. Thus, the circuitry takes less space as an integrated circuit.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
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patent: WO
Chang Wanli
Jefferson David
Altera Corporation
Cahill Steven J.
Le Thien M.
Paik Steven S.
Townsend and Townsend / and Crew LLP
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