High speed centralized switch matrix for a programmable logic de
High speed dynamic differential logic circuit employing capacita
High speed interface for a programmable interconnect circuit
High speed mask register for a configurable cellular array
High speed pipeline method and apparatus
High speed PLD "AND" array with separate nonvolatile memory
High speed product term allocation structure supporting logic it
High speed product term assignment for output enable, clock, inv
High speed programmable logic architecture
High speed programmable logic architecture
High speed programmable logic architecture
High speed programmable logic architecture
High speed tristate bus with multiplexers for selecting bus driv
High speed zero DC power programmable logic device (PLD)...
High speed, low noise output buffer with non-identical pairs of
High speed, low power macrocell
High-density erasable programmable logic device architecture usi
High-density erasable programmable logic device architecture usi
High-density erasable programmable logic device architecture usi
High-density programmable logic device with flexible local...