High speed interface for a programmable interconnect circuit

Details High speed interface for a programmable interconnect circuit High speed interface for a programmable interconnect circuit

2001-12-14

2003-11-18

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S037000, C326S042000, C326S101000

Reexamination Certificate

active

06650141

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to programmable semiconductor circuits, and more particularly to the input and output of data through such a circuit.
DESCRIPTION OF RELATED ART
In-system-programmable interconnect devices permit a user to programmably route signals between pins of the device. For example, Lattice Semiconductor Corp. currently manufactures an ispGDX® family of programmable interconnect devices having a non-volatile E
2
CMOS® in-system-programmable crossbar switch matrix for programmable switching, interconnect, and jumper functions. Each pin of the ispGDX® device is associated with an input/output (I/O) circuit that programmably couples to other I/O circuits through a routing structure denoted as a global routing pool (GRP). The I/O circuits contain registers allowing the input and output signals on the associated pins to be selectively registered.
Referring now to
FIG. 1
, an input/output circuit
10
for an ispGDX® device couples to a 4:1 multiplexer (Mux)
12
that receives signals A, B, C, and D from four different routing structures, GRP_A, GRP_B, GRP_C, and GRP_D, (not illustrated) respectively. Each routing structure corresponds to a given quadrant (a side of the integrated circuit) for the device. Accordingly, GRP_A receives the input signals from I/O pins
20
in quadrant A, GRP_B receives the input signals from I/O pins
20
in quadrant B, and so on. Input/output circuit
10
receives its input signals from its pin
20
and directs them to the appropriate global routing structure on path
19
. For example, if I/O circuit
10
is within quadrant A, path
19
would couple to GR_A.
Each routing structure is a switch matrix that may receive input signals from selected I/O circuits
10
and programmably route output signals to all I/O circuits
10
. For clarity, the individual routing structures are grouped together and jointly designated by a single routing structure
14
. A similar device or circuit is disclosed in U.S. Pat. No. 6,034,541, the contents of which are hereby incorporated by reference in their entirety.
In addition, each global routing pool has a switch matrix fused by an in-systemprogrammable non-volatile E
2
CMOS® memory bank, configured for one-way routability. A given memory cell in the volatile E
2
CMOS® memory bank controls the state of a “fuse point” in the switch matrix. The fuse point may be formed by, e.g., a pass transistor that will programmably connect an input lead of the switch matrix to an output lead of the switch matrix, depending upon the logical state (high or low) of the fuse point's memory cell. I/O pins
20
to the device are arranged in quadrants (the four sides to the chip) such that an individual routing structure receives signals from the I/O circuits
10
in a single quadrant and may distribute these signals to the I/O circuits
10
in all four quadrants. Thus, the four input signals A, B, C, and D for each Mux
12
are “quadrant” limited to originate in their respective quadrants. Note that, with respect to routing structure
14
, each I/O circuit
10
is independent and separate from the remaining I/O circuits
10
. Because routing structure
14
distributes signals independently to each I/O circuit
10
, the resulting arrangement may be denoted as “pin-oriented” or “bit-oriented” in that each I/O circuit
10
associates with a single I/O pin
20
.
Although this “bit-oriented” architecture allowed a user to programmably interconnect signals through the device, the number of fuses in the resulting global routing pool becomes prohibitive as the pin count increases. However, modem board density continues to increase, demanding an interconnect device having a suitable number of pins to interconnect the signals. Moreover, interconnect devices may be used to route signals in a backplanes for telecommunication applications where ever-increasing bandwidth and throughput requirements require increased pin counts. At the gigabit transmission rate of these applications, parallel data transmission suffers from co-channel interference and EMI effects.
To solve the problems associated with high-speed parallel data transmission, parallel data may be serialized before transmission and then de-serialized upon reception using serial transmission protocols such as a low voltage differential signaling protocol (LVDS). LVDS uses high-speed circuit techniques to provide multi-gigabit data transfers on copper interconnects and is a generic interface standard for high-speed data transmission. LVDS system features, such as synchronizing data, encoding the clock and low skew, all work together for higher performance. Skew is a big problem for sending parallel data and its clock across cables or PCB traces because the phase relation of the data and clock can be lost as a result of different travel times through the link. However, the ability to serialize parallel data into a high-speed signal with embedded clock eliminates the skew problem. The problem disappears because the clock travels with the data over the same differential pair of wires. The receiver uses a clock and data recovery circuit to extract the embeddedphase-aligned clock from the data stream. However, many serial bit streams will have periods of consecutive zeroes or ones. Because bit transitions are absent, the clock recovery component loses or cannot recover the clock during these periods. As a result, LVDS systems typically introduce data coding to ensure a suitable rate of bit transitions. For example, in a 8B/10B LVDS system, eight bits of data are encoded into a ten bit codeword, ensuring that the clock recovery component recovers the embedded clock signal. The recovered clock is then used by a data recovery component to identify the bits in the transmitted codeword.
To permit the transition between parallel and serial data transmission, serializer/deserializer (SERDES) units are incorporated at both the transmitting and receiving ends of the serial data stream. In addition, because the clock is encoded into the serial data stream, it will be incoherent to the system clock for the receiving end, necessitating a first-in-first-out (FIFO) buffer to accommodate the asynchronous reading and writing clocks.
Accordingly, there is a need in the art for an improved programmable interconnect device specialized for bus-switching applications and provides serializer/deserializer, clock data recovery, and FIFO capabilities to permit high speed serial signaling.
SUMMARY
In accordance with one aspect of the invention, a programmable semiconductor circuit includes a plurality of I/O circuits arranged into I/O blocks. Each I/O block has its own routing structure programmably coupling input signals from all the I/O circuits to the block's I/O cells. In this fashion, an I/O circuit in a given I/O block may programmably receive I/O signals from or transmit I/O signals to the I/O circuits in all the I/O blocks. The routing structure programmably routes the I/O signals according to configuration data stored in a memory device that may be insystem programmable. Each I/O circuit associates with a pin such that each I/O block has a set of pins corresponding to its I/O cells. Each I/O block associates with a serializer/de-serializer (SERDES) coupled between its I/O block and the I/O block's set of I/O pins. In addition, a first-in, first-out (FIFO) buffer couples between the SERDES and its I/O block, the SERDES being operable to recover an embedded clock signal from a serial stream of data signals coupled from a first subset of pins within the I/O block's set of pins and to convert the serial data stream into a parallel data stream using the recovered clock signal, the FIFO buffer being operable to receive the parallel data stream from the SERDES and to route the parallel data stream to I/O circuits within its I/O block.
The invention will be more fully understood upon consideration of the detailed description below, taken together with the accompanying drawings.


REFERENCES:
patent: 6011407 (2000-01-01), New
patent: 6031428 (2000-02-01), Hill
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