High speed, low noise output buffer with non-identical pairs of

Details High speed, low noise output buffer with non-identical pairs of High speed, low noise output buffer with non-identical pairs of

1990-11-02

1995-03-14

Lall, Parshotam S.

Electronic digital logic circuitry

Multifunctional or programmable

Array

395800, 326 83, 327108, H03K 1716, G06F 1300

Patent

active

053983181

ABSTRACT:
An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.

REFERENCES:
patent: 4642486 (1987-02-01), Honma et al.
patent: 4719370 (1988-01-01), Sugimoto
patent: 4992677 (1991-02-01), Ishibashi et al.
patent: 5089722 (1992-02-01), Amedeo
patent: 5140194 (1992-08-01), Okitaka

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