Balanced-delay programmable logic array and method for...

Base cell and two-dimensional array of base cells for...

Basic cell structure having a plurality of transistors for maste

Bi-directional crossbar switch with control memory for selective

Bi-directional programmable I/O cell

Bidirectional register segmented data busing

Block clock and initialization circuit for a complex high densit

Block connector splitting in logic block of a field...

Block connector splitting in logic block of a field...

Block connector splitting in logic block of a field...

Block RAM with configurable data width and parity for use in...

Block symmetrization in a field programmable gate array

Block symmetrization in a field programmable gate array

Block-oriented architecture for a programmable interconnect...

Bus operation circuit using CMOS ratio logic circuits

Bus operation circuit using CMOS ratio logic circuits

Bus structure for modularized chip with FPGA modules

Bus terminating circuit

Bypass-able carry chain in a programmable logic device