Package migration for related programmable logic devices
Parallel antifuse routing scheme (PARS) circuit and method for f
Parallel programmable antifuse field programmable gate array...
Partial reconfiguration of a programmable gate array using a...
Partially reconfigurable programmable logic device
Passage structures for use in low-voltage applications
Passgate structures for use in low-voltage applications
PCI-compatible programmable logic devices
PCI-compatible programmable logic devices
PCI-compatible programmable logic devices
PCI-compatible programmable logic devices
Periodic computation structure based on 1-input lookup tables
Periphery clock signal distribution circuitry for structured...
Periphery input/output interconnect structure
Permutable switching network with enhanced interconnectivity...
Pin selection system for microcontroller having multiplexer sele
Pinout architecture for a family of multiple segmented programma
Pipe-lined static router and scheduler for configurable logic sy
PLA architecture having improved clock signal to output timing u
PLA late signal circuitry using a specialized gap cell and PLA l