Sample and load scheme for observability of internal nodes in a

Scalable architecture for high density CPLD's having...

Scalable architecture for high density CPLDS having...

Scalable complex programmable logic device with segmented...

Scalable multiple level tab oriented interconnect architecture

Scalable non-blocking switching network for programmable logic

Scalable non-blocking switching network for programmable logic

Scalable non-blocking switching network for programmable logic

Scalable non-blocking switching network for programmable logic

Scalable non-blocking switching network for programmable logic

Scaleable padframe interface circuit for FPGA yielding improved

SCSI cable with two cable segments having a first resistor coupl

SCSI controller having output driver with slew rate control

Segmented configuration of programmable logic devices

Segmented localized conductors for programmable logic devices

Self-configuring interface circuitry, including circuitry for id

Self-reconfigurable parallel processor made from regularly-conne

Self-timed low power ratio-logic system having an input sensing

Semiconductor device

Semiconductor device having circuit blocks with mutually the...