Selecting subroutine return mechanisms
Selection of link and fall-through address using a bit in a...
Selective hardware lock disabling
Selective hardware lock disabling
Selective instruction breakpoint generation based on a count...
Selective interrupt suppression
Selective MISR data accumulation during exception processing
Selective postponement of branch target buffer (BTB) allocation
Selective signalling of later reserve location memory fault...
Selective writing of data elements from packed data based...
Selectively processing different size data in multiplier and...
Self modifying code to test all possible addressing modes
Self-priming loop execution for loop prolog instruction
Self-synchronous transfer control circuit and data driven...
Semantic processor systems and methods
Semiconductor device
Sending both a load instruction and retrieved data from a...
Sequence control circuit
Sequencer address management
Sequencer unit with instruction buffering