Sequencer unit with instruction buffering

Details Sequencer unit with instruction buffering Sequencer unit with instruction buffering

2007-08-28

2007-08-28

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

Reexamination Certificate

active

10890702

ABSTRACT:
A sequencer unit includes a first instruction processing unit, an instruction buffer and a second instruction processing unit. The first instruction processing unit is adapted for receiving and processing a stream of instructions, and for issuing, in case data is required by a certain instruction, a corresponding data read request for fetching said data. Instructions that wait for requested data are buffered in the instruction buffer. The second instruction processing unit is adapted for receiving requested data that corresponds to one of the issued data read requests, for assigning the requested data to the corresponding instructions buffered in the instruction buffer, and for processing said instructions in order to generate an output data stream.

REFERENCES:
patent: 4095269 (1978-06-01), Kawabe et al.
patent: 6070235 (2000-05-01), Cheong et al.
patent: 6249880 (2001-06-01), Shelly et al.
patent: 6978330 (2005-12-01), Joffe et al.
patent: 7039841 (2006-05-01), Cullen et al.
patent: 7096347 (2006-08-01), Moore
patent: 0 376 004 (1990-04-01), None
JP Patent Abstract 61169778, Jul. 31, 1986, NEC Corp.
JP Patent Abstract 59003647, Jan. 10, 1984, Fujitsu Ltd.

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