Selective hardware lock disabling

Details Selective hardware lock disabling Selective hardware lock disabling

2007-02-23

2009-11-03

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

C712S218000

Reexamination Certificate

active

07613908

ABSTRACT:
Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.

REFERENCES:
patent: 5721855 (1998-02-01), Hinton et al.
patent: 6862664 (2005-03-01), Tremblay et al.
Rajwar, R. etal. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, 2001, IEEE, pp. 294-305.
Rajwar & Goodman, Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, Dec. 3-5, 2001, 34th International Symposium on Microarchitecture, Austin Texas.

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