Selective interrupt suppression

Details Selective interrupt suppression Selective interrupt suppression

2003-03-10

2009-06-09

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C710S262000

Reexamination Certificate

active

07546446

ABSTRACT:
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies that interrupt processing be suppressed until execution of the extended instruction is completed, where the extended instruction prescribes an operation to be performed according to an existing instruction set. The extended prefix tag is an otherwise architecturally specified opcode within an existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and completes execution of the corresponding micro instructions prior to processing a pending interrupt.

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