Target branch prediction using a plurality of tables

Target instructions prefetch cache

Target-frequency based indirect jump prediction for...

Techniques for hardware-assisted multi-threaded processing

Techniques for reducing the rate of instruction issuance

Techniques for storing instructions and related information...

Ternary content addressable memory based multi-dimensional...

Test and skip processor instruction having at least one...

Thread migration control based on prediction of migration...

Thread performance analysis by monitoring processor performance

Thread suspension system and method

Thread switch logic in a multiple-thread processor

Thread switch on blocked load or store using instruction...

Thread-specific branch prediction by logically splitting...

Three input arithmetic logic unit with barrel rotator and mask g

Three input arithmetic logic unit with shifter and mask generato

Three state branch history using one bit in a branch...

Threshold-based load address prediction and new thread...

Throwing one selected representative exception among...

Time-multiplexed speculative multi-threading to support...