Selective hardware lock disabling

Electrical computers and digital processing systems: processing – Processing control

Reexamination Certificate

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C712S225000

Reexamination Certificate

active

07975129

ABSTRACT:
Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.

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Rajwar, Ravi , Speculation-Based Techniques for Transactional Lock-Free Execution of Lock Based Programs, 2002, Univerisity of Wisconsin-Madison, 224 pages.
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Rajwar & Goodman, Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, Dec. 3-5, 2001, 34th International Symposium on Microarchitecture, Austin Texas.

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