N-wide add-compare-select instruction
Native copy instruction for file-access processor with...
Near-orthogonal dual-MAC instruction set architecture with...
Network processor which makes thread execution control...
Networked processor for a pipeline architecture
Non-blocking, multi-context pipelined processor
Non-destructive sideband reading of processor state information
Non-speculative instruction fetch in speculative processing
Number of pipeline stages and loop length related counter differ