General purpose processor having a variable bitwidth
General purpose register file architecture for aligned simd
Generating stop indicators during vector processing
Generation of modified command sequence from original...
Generation of modified commands repeatedly from feedback or...
Generation of multiple checkpoints in a processor that...
Global history branch prediction updating responsive to...
Global history vector recovery circuits and methods and...
Globally observing load operations prior to fence...
Globally or selectively disabling branch history table operation
GPIB system and method which provides asynchronous event notific
Graphical interface for grouping concurrent computing units...