Backing out of a processor architectural state

Backing Register File for processors

Backing store buffer for the register save engine of a...

Basic block cache microprocessor with instruction history...

Basic block oriented trace cache utilizing a basic block...

Bi-directional return register stack recovery from...

Bi-level branch target prediction scheme with fetch address pred

Bi-level branch target prediction scheme with mux select predict

Bit field extraction with sign or zero extend

Bit field extraction with sign or zero extend

Block-based branch target buffer

Branch and return on blocked load or store

Branch control memory

Branch instruction control apparatus and control method

Branch instruction for processor with branching dependent on...

Branch instruction for processor with branching dependent on...

Branch instruction handling in a self-timed marking system

Branch instruction mechanism for processor

Branch instruction prediction method

Branch instructions with decoupled condition and address