1 Method to prevent pipeline stalls in superscalar stack...
Abort prioritization in a trace-based processor
Accelerating vector processing using plural sequencers to...
Accessing a test condition for multiple sub-operations using...
Accessing items of architectural state from a register cache...
Accessing tables in memory banks using load and store...
Accumulator read port arbitration logic
Accuracy of multiple branch prediction schemes
Accurate high speed digital signal processor
Acquiring instruction addresses associated with performance...
Activating a design test mode in a graphics card having...
Adapter for a microprocessor
Adaptive execution cycle control method for enhanced...
Adaptive microprocessor with dynamically reconfigurable microcod
Address calculation instruction within data processing systems
Address calculation unit for an object oriented processor...
Address calculation unit for an object oriented processor...
Adjustable cycle pipeline system and method
Aggressive store merging in a processor that supports...
Aligning load/store data using rotate, mask,...