Fault recovery on a massively parallel computer system to...

Feedback mechanism for dynamic predication of indirect jumps

Fencing off instruction buffer until re-circulation of...

Fetch branch architecture for reducing branch penalty...

Fetch director employing barrel-incrementer-based...

Filter micro-coded accelerator

Fixed length memory to memory arithmetic and architecture...

Fixed length memory to memory arithmetic and architecture...

Fixed point unit pipeline allowing partial instruction...

Flag optimization of a trace

Flags handling for system call instructions

Floating point and multimedia unit with data type reclassificati

Floating point exception handling in pipelined processor...

Floating point NaN comparison

Floating point only SIMD instruction set architecture...

Floating point operation system which determines an exchange ins

Floating point stack manipulation using a register map and specu

Floating point status/control register encodings for...

Floating point unit pipeline synchronized with processor...

Floating point unit pipeline synchronized with processor...