Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2011-08-09
2011-08-09
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
Reexamination Certificate
active
07996662
ABSTRACT:
In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an instruction operation and a value representing an update for the SCR. The value includes at least a first encoding that represents an update to a plurality of bits in the SCR, and a first number of bits in the plurality of bits is greater than a second number of bits in the first encoding. The decode circuit is coupled to receive the first encoding from a first storage location responsive to retirement of a first instruction operation assigned to use the first storage location as a destination, and is configured to decode the first encoding and generate the plurality of bits. The decode circuit is configured to update the SCR.
REFERENCES:
patent: 5673426 (1997-09-01), Shen et al.
patent: 5692169 (1997-11-01), Kathail et al.
patent: 5778219 (1998-07-01), Amerson et al.
patent: 5867683 (1999-02-01), Witt et al.
patent: 5987600 (1999-11-01), Papworth et al.
patent: 6021488 (2000-02-01), Eisen et al.
patent: 6049868 (2000-04-01), Panwar
patent: 6112019 (2000-08-01), Chamdani et al.
patent: 6125443 (2000-09-01), Takahashi
patent: 6216222 (2001-04-01), Hinds et al.
patent: 6223278 (2001-04-01), Morrison
patent: 6266763 (2001-07-01), Witt et al.
patent: 6484251 (2002-11-01), McDonald et al.
John Paul Shen & Mikko H. Lipasti; Modern Processor Design: Fundamentals of Superscalar Processors; 2003; McGraw Hilll Beta Edition; pp. 159-161.
“PowerPC User Instruction Set Architecture,” Book I, Version 2.01, Sep. 2003, IBM, pp. 81-116.
Lien Wei-Han
Murray Daniel C.
Sugisawa Junji
Apple Inc.
Chan Eddie
Faherty Corey
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
LandOfFree
Floating point status/control register encodings for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating point status/control register encodings for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating point status/control register encodings for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2658963