Floating point only SIMD instruction set architecture...

Details Floating point only SIMD instruction set architecture... Floating point only SIMD instruction set architecture...

2011-03-01

2011-03-01

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S022000

Reexamination Certificate

active

07900025

ABSTRACT:
Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the execution unit. The execution unit has logic that implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA). The floating point vector registers of the vector register file store both scalar and floating point values as vectors having a plurality of vector elements. The processor may be part of a data processing system.

REFERENCES:
patent: 3389379 (1968-06-01), Erickson et al.
patent: 5646875 (1997-07-01), Taborn et al.
patent: 5933650 (1999-08-01), van Hook et al.
patent: 6317824 (2001-11-01), Thakkar et al.
patent: 6839828 (2005-01-01), Gschwind et al.
patent: 2007/0011441 (2007-01-01), Eichenberger et al.
patent: 2008/0034357 (2008-02-01), Gschwind
patent: 2009/0037694 (2009-02-01), Luick et al.
patent: 2009/0049113 (2009-02-01), Muff et al.
patent: 2009/0198966 (2009-08-01), Gschwind et al.
patent: 2009/0198977 (2009-08-01), Gschwind et al.
patent: 2009/0307656 (2009-12-01), Eichenberger et al.
patent: 2010/0095086 (2010-04-01), Eichenberger et al.
patent: 2010/0095087 (2010-04-01), Eichenberger et al.
patent: 2010/0095098 (2010-04-01), Gschwind
patent: 2010/0095285 (2010-04-01), Gschwind
“Power ISA, Version 2.04”, IBM Corporation, Apr. 3, 2007, accessible at http://www.power.org/resources/downloads/PowerISA—203.Public.pdf, 874 pages (21 pages submitted herewith).
“Synergistic Processor Unit Instruction Set Architecture, Version 1.2”, IBM Corporation, Jan. 27, 2007, http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/76CA6C7304210F3987257060006F2C44/$file/SPU—ISA—v1.2—27Jan2007—pub.pdf, 279 pages.
“The VIS Instruction Set, Version 1.0”, Sun Microsystems Inc., A White Paper, Jun. 2002, 34 pages.
Bachega, Leonardo et al., “A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design”, Proceedings of the 13th International Conference on Parallel Architecture and Compilation Techniques (PACT'04), pp. 1-12, 2004.
Eichenberger, Alexandre E. et al., “Optimizing Compiler for a CELL Processor”, IEEE, PACT'05, 2005, http://domino.research.ibm.com/comm/research—projects.nsf/pages/cellcompiler.refs.html/$FILE/paper-eichen-pact05.pdf, 12 pages.
Eichenberger, Alexandre E. et al., “Using advanced compiler technology to exploit the performance of the Cell Broadband Engine architecture”, IBM Corporation, IBM Systems Journal, vol. 45, No. 1, 2006, http:www.research.ibm.com/journals/sj/451/eichenberger.pdf, pp. 59-84.
Gibbs, Ben et al., “IBM eServer BladeCenter JS20 PowerPc 970 Programming Environment”, Jan. 2005, www.redbooks.ibm.com/redpapers/pdfs/redp3890.pdf, 140 pages.
Gschwind, Michael et al., “Synergistic Processing in Cell's Multicore Architecture”, IEEE Micro, vol. 26, No. 2, 2006, pp. 10-24.
Thompson, Tom, “AltiVec Revealed”, MACTECH, vol. 15, No. 7, 1999, http://www.mactech.com/articles/mactech/Vol.15/15.07/AltiVecRevealed/, 19 pages.
Wait, C.D., “IBM PowerPC 440 FPU with complex-arithmetic extensions”, IBM Corporation, IBM J. Res. & Dev., vol. 49, No. 2/3, Mar./May 2005, http://www.research.ibm.com/journal/rd/492/wait.pdf, pp. 249-254.
Bik, Aart J.C. et al., “Automatic Intra-Register Vectorization for the Intel Architecture”, International Journal of Parallel Programming, vol. 30, No. 2, Apr. 2002, pp. 65-98.
Eichenberger, Alexandre et al., “Vectorization for SIMD Architectures with Alignment Constraints”, Proceedings of the Conference on Programming Language Design and Implementation (PLDI), 2004, 12 pages.
Wu, Peng et al., “An Integrated Simdization Framework Using Virtual Vectors”, Proceedings of the International Conference on Supercomputing (ICS), 2005, 10 pages.
Wu, Peng et al., “Efficient SIMD Code Generation for Runtime Alignment and Length Conversion”, Proceedings of the International Symposium on Code Generation and Optimization (CGO), 2005, 12 pages.
“Intel 64 and IA-32 Architectures Software Developer's Manual, vol. 1: Basic Architecture”, Intel Corporation, Sep. 2008, http://downioad.intel.com/design/processor/manuals/253665.pdf, 496 pages. (23 pages submitted Herewith.).
Gschwind, Michael K., “Array Reference Safety Analysis in the Presence of Loops with Conditional Control Flow”, U.S. Appl. No. 12/250,562, filed Oct. 14, 2008.
Gschwind, Michael K., “Generating and Executing Programs for a Floating Point Single Instruction Multiple Data Instruction Set Architecture”, U.S. Appl. No. 12/250,581, filed Oct. 14, 2008.
Eichenberger, Alexandre E. et al., “Dynamic Data Driven Alignment and Data Formatting in a Floating-Point SIMD Architecture”, U.S. Appl. No. 12/250,584, filed Oct. 14, 2008.
Eichenberger, Alexandre E. et al., “Dynamically Aligning Enhanced Precision Vectors Based on Addresses Corresponding to Reduced Precision Vectors”, U.S. Appl. No. 12/250,599, filed Oct. 14, 2008.
U.S. Appl. No. 12/250,562, Image File Wrapper printed Jul. 16, 2010, 2 pages.
U.S. Appl. No. 12/250,581, Image File Wrapper printed Jul. 16, 2010, 2 pages.
U.S. Appl. No. 12/250,584, Image File Wrapper printed Jul. 16, 2010, 2 pages.
U.S. Appl. No. 12/250,599, Image File Wrapper printed Jul. 16, 2010, 2 pages.
Notice of Allowance mailed Aug. 27, 2010 for U.S. Appl. No. 12/250,599, 6 pages.
Response to Office Action filed Aug. 20, 2010, U.S. Appl. No. 12/250,599, 16 pages.

Affiliated with

Also associated with

Rating

Floating point only SIMD instruction set architecture... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Floating point only SIMD instruction set architecture..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating point only SIMD instruction set architecture... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2726655