Fetch director employing barrel-incrementer-based...

Details Fetch director employing barrel-incrementer-based... Fetch director employing barrel-incrementer-based...

2005-03-22

2009-02-10

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Processing sequence control

C718S103000

Reexamination Certificate

active

07490230

ABSTRACT:
A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit adds a first addend to a 1-bit left-rotated version of a second addend to generate a sum and a carry-out bit. The circuit includes the carry-out bit as a carry-in bit of the add to generate the sum. The sum is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority. The threads are selected round-robin within the highest and lowest priorities.

REFERENCES:
patent: 4126895 (1978-11-01), Weemaes et al.
patent: 4924380 (1990-05-01), McKinney et al.
patent: 5095460 (1992-03-01), Rodeheffer
patent: 5276887 (1994-01-01), Haynie
patent: 5309382 (1994-05-01), Tamura et al.
patent: 5357512 (1994-10-01), Khaira et al.
patent: 5528513 (1996-06-01), Vaitzblit et al.
patent: 5734877 (1998-03-01), Ries et al.
patent: 5745778 (1998-04-01), Alfieri
patent: 5793993 (1998-08-01), Broedner et al.
patent: 5832278 (1998-11-01), Pham
patent: 5898694 (1999-04-01), Ilyadis et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5938742 (1999-08-01), Faddell et al.
patent: 6032218 (2000-02-01), Lewin et al.
patent: 6073159 (2000-06-01), Emer et al.
patent: 6094435 (2000-07-01), Hoffman et al.
patent: 6101193 (2000-08-01), Ohba
patent: 6105051 (2000-08-01), Borkenhagen et al.
patent: 6105053 (2000-08-01), Kimmel et al.
patent: 6163827 (2000-12-01), Viswanadham et al.
patent: 6170051 (2001-01-01), Dowling
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6272520 (2001-08-01), Sharangpani et al.
patent: 6272579 (2001-08-01), Lentz et al.
patent: 6295600 (2001-09-01), Parady
patent: 6385715 (2002-05-01), Merchant et al.
patent: 6389449 (2002-05-01), Nemirovsky et al.
patent: 6434155 (2002-08-01), Jones et al.
patent: 6470016 (2002-10-01), Kalkunte et al.
patent: 6477562 (2002-11-01), Nemirovsky et al.
patent: 6516369 (2003-02-01), Bredin
patent: 6542921 (2003-04-01), Sager
patent: 6549930 (2003-04-01), Chrysos et al.
patent: 6556571 (2003-04-01), Shahrier et al.
patent: 6563818 (2003-05-01), Sang et al.
patent: 6567839 (2003-05-01), Borkenhagen et al.
patent: 6633939 (2003-10-01), Butta' et al.
patent: 6647449 (2003-11-01), Watts
patent: 6658447 (2003-12-01), Cota-Robles
patent: 6665760 (2003-12-01), Dotson
patent: 6721874 (2004-04-01), Le et al.
patent: 6754736 (2004-06-01), Ogawa et al.
patent: 6792446 (2004-09-01), Merchant et al.
patent: 6810426 (2004-10-01), Mysore et al.
patent: 6868529 (2005-03-01), Frannhagen
patent: 7007153 (2006-02-01), Berenbaum et al.
patent: 7015913 (2006-03-01), Lindholm et al.
patent: 7035997 (2006-04-01), Musoll et al.
patent: 7051189 (2006-05-01), Warnes
patent: 7120714 (2006-10-01), O'Connor et al.
patent: 7139898 (2006-11-01), Nemirovsky et al.
patent: 7185178 (2007-02-01), Barreh et al.
patent: 7269712 (2007-09-01), Cho
patent: 2002/0062435 (2002-05-01), Nemirovsky et al.
patent: 2003/0018686 (2003-01-01), Kalafatis et al.
patent: 2003/0028816 (2003-02-01), Bacon
patent: 2003/0182536 (2003-09-01), Teruyama
patent: 2003/0233394 (2003-12-01), Rudd et al.
patent: 2004/0060052 (2004-03-01), Brown et al.
patent: 2004/0128448 (2004-07-01), Stark et al.
patent: 2004/0139441 (2004-07-01), Kaburaki et al.
patent: 2004/0215945 (2004-10-01), Burky et al.
patent: 2004/0215947 (2004-10-01), Ward et al.
patent: 2004/0216105 (2004-10-01), Burky et al.
patent: 2004/0216106 (2004-10-01), Kalla et al.
patent: 2005/0076189 (2005-04-01), Wittenburg et al.
patent: 2005/0138328 (2005-06-01), Moy et al.
patent: 2006/0004989 (2006-01-01), Golla
patent: 2006/0004995 (2006-01-01), Hetherington et al.
patent: 2006/0095732 (2006-05-01), Tran et al.
patent: 2006/0123420 (2006-06-01), Nishikawa
patent: 2006/0179194 (2006-08-01), Jensen et al.
patent: 2006/0179274 (2006-08-01), Jones et al.
patent: 2006/0179279 (2006-08-01), Jones et al.
patent: 2006/0179280 (2006-08-01), Jensen et al.
patent: 2006/0179281 (2006-08-01), Jensen et al.
patent: 2006/0179283 (2006-08-01), Jensen et al.
patent: 2006/0179284 (2006-08-01), Jensen et al.
patent: 2006/0179439 (2006-08-01), Jones et al.
patent: 2006/0206692 (2006-09-01), Jensen
patent: 2007/0089112 (2007-04-01), Jensen
patent: 2007/0113053 (2007-05-01), Jensen et al.
patent: 2007/0204137 (2007-08-01), Tran
patent: 2008/0069115 (2008-03-01), Jensen
patent: 2008/0069128 (2008-03-01), Jensen
patent: 2008/0069129 (2008-03-01), Jensen
patent: 2008/0069130 (2008-03-01), Jensen
patent: 10110504 (2001-10-01), None
patent: 1351117 (2003-08-01), None
patent: WO02/39269 (2002-05-01), None
“RTOS Operations Put in Hardware IP”, Electronic Engineering Times article, posted Jan. 17, 2005 by Ron Wilson. http://www.eetasia.com/article—content.php3?article—id=8800356670.
“A Survey of Processors With Explicit Multithreading”, in ACM Computing Surverys, vol. 35, No. 1, Mar. 2003, pp. 29-63 by Theo Ungerer, et al.
“Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations”, from Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, 1994 by Laudon et al.
“Instruction Recycling on a Multiple-Path Processor”, in 5th International Symposium on High Performance Computer Architecture, Jan. 1999 by Wallace et al.
MIPS SOC-it 101 System Controller Family User's Manual, MD0163, Rev. 01.05, May 18, 2004, p. 49-50.
MIPS SOC-it 101 System Controller Family Integrator's Guide, MD0162, Rev. 01.03, May 18, 2004, p. 31-35.
MIPS SOC-it 101 System Controller Family Datasheet, MD0164, Rev. 01.04, May 19, 2004, p. 25-26.
Shin et al. “Dynamic Scheduling Issues in SMT Architectures.” Parallel and Distributed Processing Symposium, 2003. Apr. 22, 2003. pp. 77-84. XP010645608. ISBN: 0-76950-1926-1.
Fiske et al. “Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors.” Future Generations Computer Systems, Elsevier Science Publishers. Amsterdam, NL. vol. 11, No. 6, Oct. 1995. pp. 503-518, XP004002214 ISSN: 0167-739X.
Ilhyun et al. “Understanding Sceduling Replay Schemes.” High Performance Computer Architecture. 2004. Department of Electrical and Computer Engineering. University of Wisconsin-Madison. Feb. 14, 2004. XP010778841. ISBN: 0-7695-2053-7.
Sigmund et al. “On Speculation Control in Simultaneous Multithreaded Processors.” Journal of Universal Computer Science. vol. 7, No. 9. Sep. 28, 2001. pp. 848-868. XP009069084. ISSN 0948-695X.
Hennessy et al. “Computer Architecture—A Quantative Approach, 3rd edition.” Morgan Kaufmann, USA. XP002388271. ISBN: 1558607242. pp. 181-187.
Sazeides, Yiannakis. “Modeling Value Speculation.” High-Performance Computer Architecture, 2002. Feb. 2, 2002. pp. 189-200. XP010588723. ISBN: 07695-1525-B.
“Mercury Computer Systems Introduces The MC432 Serial RapidIO Switch With a Breakthrough Feature Set.” connectiviyZone Products for the week of Dec. 12, 2005. Downloaded on Aug. 18, 2006 from http://www.analogzone.com/iop—1212.htm.
“Tundra Launches Industry's First Serial RapidIO Switch.” connectivityZone Products for the week of Feb. 14, 2005. Downloaded on Aug. 18, 2006 from http://www.analogzone.com/iop—0214.htm.
“Tsi568A.ȁ

Affiliated with

Also associated with

Rating

Fetch director employing barrel-incrementer-based... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fetch director employing barrel-incrementer-based..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fetch director employing barrel-incrementer-based... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4082391