Flag optimization of a trace

Electrical computers and digital processing systems: processing – Processing control

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07849292

ABSTRACT:
A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include locating an operation, if any, that is next within the sequence of operations and setting a current operation to be that operation. The current operation is processed as follows: a) de-activating, if not already de-activated, a consumed indicator associated with the current operation; and b) when the current operation is of the producer type, then activating, if not already activated, a producer indicator associated with the current operation, and locating a first set of operations, if any, that i) are earlier in the sequence of operations than the current operation, ii) have their associated producer indicator activated, and iii) have their associated consumed indicator de-activated, and then de-activating the producer indicator associated with each operation in the first set. When the current operation is of the consumer type, then locating a second set of operations, if any, that are earlier in the sequence of operations than the current operation, and then activating, if not already activated, the consumed indicator associated with each operation in the second set.

REFERENCES:
patent: 4912707 (1990-03-01), Kogge et al.
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5491793 (1996-02-01), Somasundaram et al.
patent: 5568380 (1996-10-01), Brodnax et al.
patent: 5632023 (1997-05-01), White et al.
patent: 5649136 (1997-07-01), Shen et al.
patent: 5944841 (1999-08-01), Christie
patent: 6014742 (2000-01-01), Krick et al.
patent: 6018786 (2000-01-01), Krick et al.
patent: 6031992 (2000-02-01), Cmelik et al.
patent: 6055630 (2000-04-01), D'Sa et al.
patent: 6073213 (2000-06-01), Peled et al.
patent: 6076144 (2000-06-01), Peled et al.
patent: 6115809 (2000-09-01), Mattson, Jr. et al.
patent: 6170038 (2001-01-01), Krick et al.
patent: 6185660 (2001-02-01), Mulla et al.
patent: 6185675 (2001-02-01), Kranich et al.
patent: 6189141 (2001-02-01), Benitez et al.
patent: 6205545 (2001-03-01), Shah et al.
patent: 6216206 (2001-04-01), Peled et al.
patent: 6351844 (2002-02-01), Bala
patent: 6442674 (2002-08-01), Lee et al.
patent: 6449714 (2002-09-01), Sinharoy
patent: 6538997 (2003-03-01), Wang et al.
patent: 6604060 (2003-08-01), Ryan et al.
patent: 6609189 (2003-08-01), Kuszmaul et al.
patent: 6671766 (2003-12-01), Vandenbergh et al.
patent: 6799263 (2004-09-01), Morris et al.
patent: 6826182 (2004-11-01), Parthasarathy
patent: 6895460 (2005-05-01), Desoli et al.
patent: 6950924 (2005-09-01), Miller et al.
patent: 6988190 (2006-01-01), Park
patent: 7003629 (2006-02-01), Alsup
patent: 7010648 (2006-03-01), Kadambi et al.
patent: 7133969 (2006-11-01), Alsup et al.
patent: 7136992 (2006-11-01), Maiyuran et al.
patent: 7139902 (2006-11-01), Lee
patent: 7213126 (2007-05-01), Smaus et al.
patent: 7360024 (2008-04-01), Hironaka et al.
patent: 7366875 (2008-04-01), Rasche et al.
patent: 7415598 (2008-08-01), Dos Remedios
patent: 7546420 (2009-06-01), Shar et al.
patent: 7594111 (2009-09-01), Kiriansky et al.
patent: 7606975 (2009-10-01), Shar et al.
patent: 2001/0032307 (2001-10-01), Rohlman et al.
patent: 2002/0095553 (2002-07-01), Mendelson et al.
patent: 2002/0144101 (2002-10-01), Wang et al.
patent: 2003/0005271 (2003-01-01), Hsu et al.
patent: 2003/0084375 (2003-05-01), Moore et al.
patent: 2004/0015627 (2004-01-01), Desoli et al.
patent: 2004/0083352 (2004-04-01), Lee
patent: 2004/0107336 (2004-06-01), Douglas et al.
patent: 2004/0193857 (2004-09-01), Miller et al.
patent: 2005/0108719 (2005-05-01), Need et al.
patent: 2005/0125632 (2005-06-01), Alsup et al.
patent: 2005/0289324 (2005-12-01), Miller et al.
patent: 2005/0289529 (2005-12-01), Almog et al.
patent: 2006/0179346 (2006-08-01), Bishop et al.
patent: 2007/0157007 (2007-07-01), Jourdan et al.
Almog, Y. et al., Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture, Proceedings of the International Symposium on Code Generation and Optimization, 2004 (12 pages).
Chaparro, P. et al., Distributing the Fronted for Temperature Reduction, Proceedings of the 11th Symposium on High-Performace Computer Architecture, Feb. 12-16, 2005 (10 pages).
Colwell, R. P. et al., A VLIW Architecture for a Trace Scheduling Compiler, 1987, pp. 180-192 (13 pages).
Fisher, J. A., Trace Scheduling: A Technique for Global Microcode Compaction, IEEE Transactions on Computers, vol. C-30, No. 7, Jul. 1981, pp. 478-490 (13 pages).
Friendly, D. et al, Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors, Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture, Nov. 30-Dec. 2, 1998, pp. 173-181 (9 pages).
Grunwald, D. and Ghiasi, S., Microarchitectural Denial of Service : Insuring Microarchitectural Fairness, Proceedings of the 35th Annual IEEE/ACM International Symposium on Microarchitecture, Nov. 18-22, 2002 (10 pages).
Hinton, G. et al., The Microarchitecture of the Pentium 4 Processor, Intel Technology Journal Q1, 2001 (12 pages).
IBM Technical Disclosure Bulletin, Grouping of Instructions, v. 38, n. 8, Aug. 1, 1995, pp. 531-534 (4 pages).
Katevenis, E. G., Reduced Instruction Set Computer Architectures for VLSI, Berkley, California 1983, pp. 67-68 and 190 (7 pages).
Rotenberg, E., Bennett, S., and Smith, J. E., Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching, In Proceedings of the 29th Annual International Symposium on Microarchitecture, Dec. 2-4, 1996, Paris, France (11 pages).
Slechta, B. et al, Dynamic Optimization of Micro-Operations, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, Feb. 8-12, 2003 (12 pages).
Smith, J. E. and Pleszkun, A. R., Implementation of Precise Interrupts in Pipelined Processors, Proc. Computer Architecture, 1985 (15 pages).
Tremblay, M., High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback, Los Angeles, California, Sep. 1991, pp. 72-74, 81, 89-90, 102-104 and 246 (14 pages).
Vijaykumar, T. N., et al., Speculative Versioning Cache, IEEE Transaction on Parallel and Distributed Systems, vol. 12, No. 12, Dec. 2001, pp. 1305-1317 (13 pages).
Patel, S., Lumetta, S., “rePlay: A Hardware Framework for Dynamic Optimization, IEEE Transactions on Computers”, vol. 50, No. 6, Jun. 2001 (26 pages).
Tanenbaum, A. S., Structured Computer Organization, Fourth Edition, Prentice Hall, Inc. 1984 (21 pages).
Patel S. J. et al., Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing, IEEE, 1998, pp. 262-271.
Tanenbaum, A. S., Structured Computer Organization, Second Edition, Prentice Hall, Inc. 1984, pp. 10-12.
Eric Rotenberg, James E. Smith, Control Independence in Trace Processors, Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, p. 4-15, Nov. 16-18, 1999, Haifa, Israel.
Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, Jim Smith, Trace Processors, Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, p. 138-148, Dec. 1-3, 1997, Research Triangle Park, North Carolina, United States.
Quinn Jacobson, Eric Rotenberg, James E. Smith, Path-Based Next Trace Prediction, Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, p. 14-23, Dec. 1-3, 1997, Research Triangle Park, North Carolina, United States.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Flag optimization of a trace does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flag optimization of a trace, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flag optimization of a trace will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4218213

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.