Packet processing validation
Parallel intrusion search in hierarchical VLSI designs with...
Pattern layout of integrated circuit
Pattern writing circuit self-diagnosis method for charged...
Performing abstraction-refinement using a...
Pipeline architecture for maximum a posteriori (MAP) decoders
Place-and-route layout method with same footprint cells
Placement and routing using inhibited overlap of expanded areas
Placement driven control set resynthesis
Placement driven routing
Placement of I/O blocks within I/O banks using an integer...
Placing complex function blocks on a programmable integrated...
Port assignment in hierarchical designs by abstracting macro...
Post-routing power supply modification for an integrated...
Power aware asynchronous circuits
Power estimation in high-level modeling systems
Power managers for an integrated circuit
Power mesh arrangement method utilized in an integrated...
Power mesh for multiple frequency operation of semiconductor...
Power network stacked via removal for congestion reduction