Power estimation in high-level modeling systems

Details Power estimation in high-level modeling systems Power estimation in high-level modeling systems

2009-02-20

2011-12-20

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S106000

Reexamination Certificate

active

08082530

ABSTRACT:
A computer-implemented method of estimating power usage for high-level blocks of a high-level modeling system (HLMS) circuit design can include generating a low-level circuit design from the HLMS circuit design. The method can include simulating the low-level circuit design and storing power usage data, from the simulating, for each of a plurality of circuit elements of the low-level circuit design. The circuit elements can be correlated with the high-level blocks of the HLMS circuit design. A power query of a selected block of the HLMS circuit design can be received and a measure of power usage for the selected high-level block can be determined according to the power usage data for selected ones of the plurality of circuit elements correlated with the selected high-level block. The measure of power usage for the selected high-level block can be output.

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