Pipeline architecture for maximum a posteriori (MAP) decoders

Details Pipeline architecture for maximum a posteriori (MAP) decoders Pipeline architecture for maximum a posteriori (MAP) decoders

2005-11-01

2005-11-01

Decady, Albert (Department: 2133)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C714S791000

Reexamination Certificate

active

06961921

ABSTRACT:
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is read from memory on the same clock edge that the new forward metric is written to the same memory location. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

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