Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-10-15
2011-11-01
Lin, Sun (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S126000, C716S130000, C716S133000
Reexamination Certificate
active
08051401
ABSTRACT:
A technique for generating a layout of an integrated circuit places standard cells in position and provides power rail conductors formed in a second metal layer overlying power connection conductors formed in a first metal layer via which the power is supplied to the standard cells. Routing connection conductors are added in the first metal layer and are permitted to pass through gaps between the power connection conductors of the first metal layer and underneath the power rail conductors of the second metal layer. Once routing has been performed, gaps between the power connection conductors of the first metal layer underlying the power rail conductors and not being used by routing connection conductors are closed so as form interrupted power rail conductors within the first meal layer.
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ARM Limited
Lin Sun
Nixon & Vanderhye P.C.
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