Placement and routing using inhibited overlap of expanded areas

Details Placement and routing using inhibited overlap of expanded areas Placement and routing using inhibited overlap of expanded areas

2011-04-19

2011-04-19

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S116000, C716S119000, C716S122000, C716S128000, C716S130000, C703S019000

Reexamination Certificate

active

07930668

ABSTRACT:
Methods of placing and routing a logic design are provided. The logic design includes logic elements and nets connecting the logic elements. A first placement and a partial routing of the logic elements and the nets of the logic design are generated. The partial routing leaves some of the nets unsuccessfully routed. An initial area associated with each of the logic elements is expanded for the logic elements that are connected to the unsuccessfully routed nets. Positions for the logic elements are determined from a linear system that reduces a total length of the nets connecting the logic elements and inhibits overlap of the areas of the logic elements. A second placement of the logic elements is generated from the positions. A complete routing of all of the nets is generated for the second placement. A specification of the second placement and the complete routing is output.

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