Place-and-route layout method with same footprint cells

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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C716S100000

Reexamination Certificate

active

07966596

ABSTRACT:
This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.

REFERENCES:
patent: 5737236 (1998-04-01), Maziasz et al.
patent: 2003/0229860 (2003-12-01), Li
patent: 2009/0064072 (2009-03-01), Lin et al.
patent: 2009/0265675 (2009-10-01), Walker et al.
patent: 2009/0271756 (2009-10-01), Penzes

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