Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-06-07
2011-06-07
Levin, Naum (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C709S226000
Reexamination Certificate
active
07958480
ABSTRACT:
A method of input/output (I/O) block placement assigned to an input/output bank includes formulating a placement algorithm using integer linear programming (ILP) and simultaneously placing single groups and Relatively Placed Module (RPM) groups of I/O blocks in the I/O bank. The method further includes determining a placeability matrix P and a binary assignment matrix X used for the ILP. The method can further eliminate all assignment matrix elements of X equal to 0 in the integer linear programming and re-index any remaining elements. The method can further place all I/O blocks according to a solution if solving of the standard ILP formulation results in a feasible solution. Optionally, the method generates a placement solution that is as close as possible to an external reference solution specified by designer. Optionally, the method analyzes which constraints were violated and generates useful error information.
REFERENCES:
patent: 5914616 (1999-06-01), Young et al.
patent: 6064819 (2000-05-01), Franssen et al.
patent: 6466049 (2002-10-01), Diba et al.
patent: 6986109 (2006-01-01), Allen et al.
patent: 7299439 (2007-11-01), Slonim et al.
patent: 7451422 (2008-11-01), Slonim et al.
patent: 7464147 (2008-12-01), Fakhouri et al.
patent: 7480884 (2009-01-01), Slonim et al.
patent: 7653884 (2010-01-01), Furnish et al.
patent: 2004/0230922 (2004-11-01), Allen et al.
patent: 2009/0031259 (2009-01-01), Gray et al.
patent: 2009/0228844 (2009-09-01), Mak et al.
Mak et al.; “On Constrained Pin-Mapping for FPGA—PCB Codesign”; IEEE; vol. 25, No. 11; Nov. 2006; pp. 2393-2400.
Koushanfar et al.; “ILP-Based Engineering Change”; DAC2002, Jun. 10-14, 2002, New Orleans, Louisiana, USA.; pp. 910-915.
Xilinx, Inc., “The Programmable Logic Data Book 2000,” published Apr. 2000, pp. 3-75 to 3-96, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, USA.
Xilinx, Inc., “Virtex-II Platform FPGA Handbook,” published Dec. 2000, pp. 33-75, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, USA.
Xilinx, Inc., “Virtex-II Pro Platform FPGA Handbook,” published Oct. 14, 2002, pp. 19-71, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, USA.
Kannan Parivallal
Slonim Victor Z.
Stenz Guenter
Cuenot Kevin T.
Levin Naum
Meles Pablo
Xilinx , Inc.
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