Five-transistor SRAM cell

Flip-flop circuit with controllable copying between slave and sc

Flip-flop detector array for minimum geometry semiconductor memo

Floating gate device with graphite floating gate

Four device SRAM cell with single bitline

FOUR TERMINAL MEMORY CELL, A TWO-TRANSISTOR SRAM CELL, A...

Four transistor static RAM cell

Four transistors static-random-access-memory cell

Four-transistor static memory cell array

Full CMOS type SRAM and method of manufacturing same

Gate array arrangement in complementary metal-oxide-semiconducto

Gate array macro cell

General purpose register circuit

Global bit line restore timing scheme and circuit

Global bit line restore timing scheme and circuit

Hardened memory cell

Hidden refresh pseudo SRAM and hidden refresh method

Hierarchical six-transistor SRAM

High density planar SRAM cell with merged transistors

High density SRAM circuit with ratio independent memory cells