Global bit line restore timing scheme and circuit

Details Global bit line restore timing scheme and circuit Global bit line restore timing scheme and circuit

2007-01-30

2007-01-30

Phung, Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S203000

Reexamination Certificate

active

11054479

ABSTRACT:
A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

REFERENCES:
patent: 5777935 (1998-07-01), Pantelakis et al.
patent: 6512712 (2003-01-01), Desai et al.
patent: 6930902 (2005-08-01), Mayer et al.

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