Flip-flop detector array for minimum geometry semiconductor memo

Details Flip-flop detector array for minimum geometry semiconductor memo Flip-flop detector array for minimum geometry semiconductor memo

1981-09-28

1983-08-30

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365205, G11C 1140

Patent

active

044020635

ABSTRACT:
This invention furnishes a minimum geometry integrated circuit arrangement of flip-flop detectors for a random access memory array in MOS (metal oxide semiconductor) technology. By "minimum geometry" is meant that these flip-flops occupy no more lateral space than the memory cells occupy even when every cell is built within a lateral space of only twice the minimum feature size, that is, a space of twice the minimum width of a metallization line.

REFERENCES:
patent: 3678473 (1972-07-01), Wahlstrom
patent: 4351034 (1982-09-01), Eaton, Jr. et al.
Electronics, "Maximizing a 64-K RAM's Operating Margins," pp. 197-201, Apr. 21, 1981.
K. J. O'Connor Case 1, Ser. No. 234,453 Filed Feb. 13, 1981.

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