FOUR TERMINAL MEMORY CELL, A TWO-TRANSISTOR SRAM CELL, A...

Details FOUR TERMINAL MEMORY CELL, A TWO-TRANSISTOR SRAM CELL, A... FOUR TERMINAL MEMORY CELL, A TWO-TRANSISTOR SRAM CELL, A...

2003-08-08

2004-11-02

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S174000, C365S177000, C365S156000

Reexamination Certificate

active

06813180

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to a four terminal memory cell, a two-transistor SRAM cell, a SRAM array, a computer system, a process for forming a SRAM cell, a process for turning a SRAM cell OFF, a process for writing a SRAM cell and a process for reading data from a SRAM cell.
BACKGROUND OF THE INVENTION
The reduction in memory cell and other circuit size required for high density static random access memories (SRAMs) and other circuitry is a continuing goal in semiconductor fabrication. SRAMs are used in applications where high-speed random access memories provide significant performance advantages over other types of random access memories, such as dynamic random access memories (DRAMs). However, because SRAMs draw greater electrical power per stored datum than DRAMs, and also because SRAM cells typically consume significantly more silicon real estate than DRAM cells, marked performance advantages are needed in order to justify the increased real estate and power budgets necessitated by inclusion of SRAMs. A typical application for SRAM is in what is known as a “cache” memory.
One or more cache memories are typically coupled to a central processing unit (CPU) or an arithmetic logic unit (ALU) in a processor module or chip in order to store recently-executed instructions and/or data of current interest. Due to the fact that many processing tasks involve repetitive calculations and thus require the processor to re-execute recently-executed instructions (on, for example, a sequence of data points), there is a high probability of locating a needed instruction in the cache memory and thus of providing that instruction more rapidly via the cache memory than is possible with other kinds of memories and/or memory management schemes. As a result, SRAMs can provide significant performance advantages, particularly in situations where large datasets are frequently manipulated.
One conventional SRAM architecture uses six transistors and is referenced as a 6T architecture. Another conventional SRAM architecture includes four transistors and two load devices, usually either resistors or PMOS active load devices. Either of these architectures results in a memory cell requiring significantly more area than a DRAM cell, but each provides significantly improved access time when compared to DRAM arrays.
One example of a more compact SRAM cell is described in “A 1.9 &mgr;m
2
Loadless CMOS Four-Transistor SRAM Cell In A 0.18-&mgr;m Logic Technology”, by K Noda et al., presented at the 1998 International Electron Devices Meeting, 1998, pp. 643-6. The SRAM cell described therein achieves dimensions of 1.04 &mgr;m×1.86 &mgr;m, or about 60 F
2
, where F is related to a minimum lithographic feature size, as is described in more detail hereinbelow with reference to FIG.
2
. While the area of this SRAM cell compares favorably to conventional SRAM cell areas (as described in Table 3 of the reference), the area of this SRAM cell is represented in the reference to be still at least three to six times that of conventional DRAM cells.
Accordingly, what is needed includes apparatus and methods for providing compact SRAM cells and memory cell arrays.
SUMMARY
In a first aspect, the present invention includes a two transistor memory cell for an 8F
2
SRAM array. The two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a gate, a source and a drain. The source is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.
In another aspect, the present invention includes a computer system. The computer system includes a central processing unit, an input interface and a memory device coupled to the central processing unit. The memory device is configured to store instructions and data for use by the central processing unit. The memory device includes a SRAM array formed from cells each including a first load device and a first ultrathin transistor having a power electrode coupled to the first load device. The cells also each include a second load device and a second ultrathin transistor including a power electrode coupled to the second load device. The first load device is merged with a control electrode of the second ultrathin transistor and vice versa.
In a further aspect, the present invention includes a process for forming a SRAM cell having an area of 8F
2
, or less, wherein F represents one-half of a minimum lithographic pitch of the SRAM cell. The process includes providing a semiconductive substrate having a first conductivity type and forming a diffusion region of a second conductivity type different than the first conductivity type in the substrate. The diffusion region is configured to act as a row address line. The process also includes forming first and second dielectric pillars on the substrate. The first and second pillars each have respective plan view areas of about F
2
and are separated by a distance of about F. One of the first and second pillars is formed atop the diffusion region and another of the first and second pillars is not formed atop the diffusion region. The process further includes forming first and second ultrathin transistors and first and second load devices in a space between the first and second pillars. The first load device is merged with the second ultrathin transistor and the second load device is merged with the first ultrathin transistor.
In a yet further aspect, the present invention includes a process for writing a SRAM cell to an ON state. The SRAM cell includes two switches. One of the two switches is coupled to a row address line and a column address line. The process includes modifying a voltage coupled to the row address line to cause a voltage applied to a control electrode of the one switch to exceed a threshold voltage for that switch.


REFERENCES:
patent: 5285687 (1994-02-01), Ringel et al.
patent: 5388068 (1995-02-01), Ghoshal et al.
patent: 5754010 (1998-05-01), Caravella et al.
patent: 5754468 (1998-05-01), Hobson
patent: 5774392 (1998-06-01), Kraus et al.
patent: 5825687 (1998-10-01), Yin
patent: 6011726 (2000-01-01), Batson et al.
patent: 6057555 (2000-05-01), Reedy et al.
patent: 6090648 (2000-07-01), Reedy et al.
patent: 6104045 (2000-08-01), Forbes et al.
patent: 6128216 (2000-10-01), Noble et al.
patent: 6184588 (2001-02-01), Kim et al.
patent: 6194759 (2001-02-01), Sano et al.
patent: 6208555 (2001-03-01), Noble
patent: 6212102 (2001-04-01), Georgakos et al.
patent: 6225165 (2001-05-01), Noble, Jr. et al.
patent: 6255165 (2001-07-01), Thurgate et al.
patent: 6265266 (2001-07-01), Dejenfelt et al.
patent: 6275433 (2001-08-01), Forbes
patent: 6287913 (2001-09-01), Agnello et al.
patent: 6342718 (2002-01-01), Noble
patent: 6448601 (2002-09-01), Forbes et al.
patent: 6449186 (2002-09-01), Noble
patent: 6459113 (2002-10-01), Morihara et al.
patent: 6519197 (2003-02-01), Forbes
patent: 6605961 (2003-08-01), Forbes
patent: 2001/0015907 (2001-08-01), Noble
patent: 2002/0028550 (2002-03-01), Moribara et al.
patent: 2003/0048656 (2003-03-01), Forbes
patent: 2003/0076721 (2003-04-01), Forbes
patent: 2003/0214840 (2003-11-01), Forbes
patent: 2004/0026697 (2004-02-01), Forbes
patent: 410335488 (1998-12-01), None
patent: 2001308298 (2001-11-01), None
Lage et al.,Advanced SRAM technology—the rate between 4T and 6T cells, Abstract(Web address—http:llpluto.ei.org), Technical Digest—Proceedings of the 1996 IEEE International Electron Devices Meeting Dec. 8-11, 1996.
Noda et al.,A 1.9-&mgr;m1Loadless CMOS Four-Transistor SRAM Cell in a 0.18-&mgr;m Logic Techno

Affiliated with

No affiliations

Also associated with

Rating

FOUR TERMINAL MEMORY CELL, A TWO-TRANSISTOR SRAM CELL, A... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FOUR TERMINAL MEMORY CELL, A TWO-TRANSISTOR SRAM CELL, A..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FOUR TERMINAL MEMORY CELL, A TWO-TRANSISTOR SRAM CELL, A... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3275393