Five-transistor SRAM cell

Details Five-transistor SRAM cell Five-transistor SRAM cell

1999-08-26

2001-03-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S230050

Reexamination Certificate

active

06205049

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to static random access memory (SRAM) cells. More specifically, the present invention relates to five transistor SRAM cells and methods for operating these cells in an array.
2. Discussion of Related Art
FIG. 1
is a circuit diagram of a conventional six-transistor SRAM cell
100
. SRAM cell
100
includes n-channel access transistors
101
-
102
, a first inverter
111
(which includes p-channel transistor
103
and n-channel transistor
104
), a second inverter
112
(which includes p-channel transistor
105
and n-channel transistor
106
), complementary bit lines
121
-
122
, and word line
123
. The operation of SRAM cell
100
is well documented in numerous resources, including, for example, Prince, Semiconductor Memories (2nd Edition, 1991), pp. 157-159. In general, SRAM cell
100
is accessed through both of access transistors
101
-
102
during read and write operations. Accessing SRAM cell
100
in this manner results in a relatively stable SRAM cell during both read and write operations. However, a relatively large layout area is required for the six transistors of SPAM cell
100
. It would therefore be desirable to have an SRAM cell that requires fewer than six transistors, but has the same stability as a six-transistor SRAM cell.
FIG. 2
is a circuit diagram of a conventional five-transistor SRAM cell
200
. As used herein, a five-transistor SRAM cell is defined as an SRAM cell that includes only five-transistors and no other circuit elements, such as diodes or resistors. SRAM cell
200
includes n-channel access transistor
201
, inverters
211
-
212
, nodes A and B, bit line
220
and word line
230
. Inverter
211
includes p-channel transistor
203
and n-channel transistor
204
. Similarly, inverter
212
includes p-channel transistor
205
and n-channel transistor
206
.
To write a logical 1 to SRAM cell
200
, the V
CC
supply voltage is applied to both bit line
220
and word line
230
. Under these conditions, n-channel access transistor
201
is turned on, and a voltage equal to V
CC
−V
TH
is applied to node A, where V
TH
is the threshold voltage of access transistor
201
.
To write a logical 0 to SRAM cell
200
, the V
CC
supply voltage is applied to word line
230
, and the V
SS
supply voltage is applied to bit line
220
. Under these conditions, n-channel access transistor
201
is turned on, and a voltage equal to the V
SS
supply voltage is applied to node A.
To read SRAM cell
200
, the V
CC
supply voltage is applied to word line
230
, and a read voltage is applied to bit line
220
. This read voltage must not be so high as to write a logical 1 to SRAM cell
200
during the read operation. Similarly, this read voltage must not be so low as to write a logical 0 to SRAM cell
200
. Normal temperature variations, voltage variations and process variations in SRAM cell
200
typically result in an inadequate margin for providing an appropriate read voltage in SRAM cell
200
.
To compensate for the inadequate margin available for the read voltage, a boosted voltage has been applied to word line
230
during a write operation. This boosted voltage is greater than the V
CC
supply voltage. During a read operation, the V
CC
supply voltage is applied to word line
230
. While this provides SRAM cell
200
with an acceptable operating margin, access transistor
201
must be fabricated with a relatively thick gate oxide in order to withstand the boosted voltage applied to word line
230
. This thicker gate oxide undesirably increases the complexity of the process used to fabricate SRAM cell
200
.
In addition, applying the boosted voltage to word line
230
necessarily results in write conditions in every SRAM cell coupled to word line
230
. Thus, the number of SRAM cells coupled to word line
230
is limited by the byte width of the associated array. That is, if the byte width of an associated array is 8-bits, then only 8 SRAM cells can be coupled to word line
230
. The resulting array is therefore much narrower than desired.
It would therefore be desirable to have a five-transistor SRAM cell that operates in a stable manner with a single voltage applied to the gate of the access transistor during both read and write operations. It would further be desirable to have a five-transistor SRAM cell that can be incorporated in an array, such that the number of SRAM cells coupled to each word line in the array is greater than the width of a byte in the array.
SUMMARY
Accordingly, the present invention provides an SRAM system that includes a five-transistor SRAM cell and a cell voltage control circuit coupled to provide power to the SRAM cell. The five-transistor SRAM cell includes an n-channel access transistor and a pair of cross-coupled inverters. The pair of cross-coupled inverters are formed by a pair of p-channel pull-up transistors and a pair of n-channel pull-down transistors that are stronger (i.e., have a greater width-to-length ratio) than the access transistor. As a result, it is relatively difficult to write a logic high value to the SRAM cell if the SRAM cell currently stores a logic low value. The cell voltage control circuit facilitates such a write operation by supplying the cross-coupled inverters with a cell voltage that is less than the V
CC
supply voltage during a write operation. In one embodiment, the cell voltage is selected to be less than the V
CC
supply voltage minus the threshold voltage of the access transistor. The cell voltage is further selected to be high enough to enable the SRAM cell to reliably store data during a write disturb condition. The lower cell voltage weakens the pull-down transistors in the SRAM cell, thereby enabling a logic high value to be easily written to the SRAM cell.
When the SRAM cell is not being written (i.e., during a read mode or a standby mode), the cell voltage control circuit supplies the cross-coupled inverters with the V
CC
supply voltage, thereby resulting in a stable SRAM cell.
The present invention further comprises methods of operating the five-transistor SRAM cell. One method includes the steps of (1) powering the SRAM cell with a V
CC
supply voltage during a read mode, (2) powering the SRAM cell with the V
CC
supply voltage during a standby mode, and (3) powering the SRAM cell with a cell voltage less than the V
CC
supply voltage during a write mode.
Another embodiment includes an SRAM system that includes an array of five-transistor SRAM cells arranged in rows and columns, and a plurality of cell voltage control circuits. Each of the cell voltage control circuits is coupled to supply power to a corresponding column of the SRAM cells. Each cell voltage control circuit provides the V
CC
supply voltage to power its corresponding column when no SRAM cells in the corresponding column are subject to a write operation. Each cell voltage control circuit further provides a cell voltage, which is less than the V
CC
supply voltage, to power its corresponding column when an SRAM cell in the column is subject to a write operation. The lower cell voltage facilitates write operations to the SRAM cells by weakening pull-down transistors in the SRAM cells during the write operation. Moreover, providing each column with a corresponding cell voltage control circuit enables the number of SRAM cells in each row to be greater than the byte-width of the array. In a variation of this embodiment, each cell voltage control circuit is coupled to supply power to a corresponding plurality of columns of SRAM cells. This advantageously reduces the required number of cell voltage control circuits.
In another embodiment, each of the cell voltage control circuits is coupled to supply power to a corresponding row of the SRAM cells. Each cell voltage control circuit provides the V
CC
supply voltage to power its corresponding row when no SRAM cells in the corresponding row are subject to a write operation. Each cell voltage control circuit further provides a cell voltage, which is less than the V
CC
supply voltage, to power i

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