Gate array macro cell

Details Gate array macro cell Gate array macro cell

1988-09-02

1991-06-25

Heckler, Thomas M.

Static information storage and retrieval

Systems using particular element

Flip-flop

364900, 3649542, 3649591, 3649655, G11C 506

Patent

active

050273191

ABSTRACT:
A gate array macro cell combines the functions of a single SRAM bit and two ROM bits in order to fully utilize all of the transistors in two CMOS gate array core cells, therein increasing the efficiency of implementing memory on a gate array. The SRAM is a six transistor memory cell and each ROM bit is provided by a P-channel field effect transistor. The SRAM and each ROM bit may be accessed separately since each bit is provided with its own word and bit lines.

REFERENCES:
patent: 4222062 (1980-09-01), Trotter et al.
patent: 4724531 (1988-02-01), Angleton et al.
patent: 4779231 (1988-10-01), Holzapfel et al.
patent: 4851892 (1989-07-01), Anderson et al.
patent: 4855803 (1989-08-01), Azumai et al.
patent: 4879688 (1989-11-01), Turner et al.
patent: 4884115 (1989-11-01), Michel et al.

Affiliated with

Also associated with

Rating

Gate array macro cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate array macro cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate array macro cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1045701