Gate array arrangement in complementary metal-oxide-semiconducto

Details Gate array arrangement in complementary metal-oxide-semiconducto Gate array arrangement in complementary metal-oxide-semiconducto

1986-12-03

1988-10-18

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365181, G11C 506

Patent

active

047792310

ABSTRACT:
A gate array arrangement provides cell zones in the form of a matrix in a core zone of a chip. Each cell zone contains a fundamental circuit which consists of six or seven transistors designed in CMOS technology and which can perform a logic function or a storage function on the basis of appropriate interconnections. The connection of the fundamental circuits to one another is carried out either by way of the fundamental circuits or by using fundamental circuits which are not used to construct memories or logic functions. On the basis of the fundamental circuits consisting of six or seven n-channel and p-channel transistors it is possible to construct one storage cell per fundamental circuit and therefore to provide memories which can be adapted to the prevailing requirements in a gate array arrangement.

REFERENCES:
patent: 3521242 (1970-07-01), Katz
patent: 4441169 (1984-04-01), Sasaki et al.
Asano et al., "Design of CMOS Masterslice Logic LSI", Electronics & Communications in Japan, vol. 66, No. 1, 1983, pp. 111-119.

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