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EEPROM memory organized in plural bit words

Static information storage and retrieval – Read/write circuit – Complementing/balancing
Patent

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EEPROM programming method

Static information storage and retrieval – Read/write circuit – Erase
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EEPROM programming switch

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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EEPROM programming switch operable at low VCC

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
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EEPROM utilizing single transistor per cell capable of both byte

Static information storage and retrieval – Read/write circuit – Erase
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Efficiency improved DRAM row redundancy circuit

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Efficient back bias (V.sub.BB) detection and control scheme for

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
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Efficient back bias (VBB) detection and control scheme for...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Efficient column redundancy techniques

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Efficient implementation of a read scheme for multi-threaded...

Static information storage and retrieval – Read/write circuit
Reexamination Certificate

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Efficient latch array initialization

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Efficient method for obtaining usable parts from a partially goo

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Efficient method of data transfer between register files and...

Static information storage and retrieval – Read/write circuit
Reexamination Certificate

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Efficient read, write methods for multi-state memory

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Efficient redundancy method for RAM circuit

Static information storage and retrieval – Read/write circuit – Multiplexing
Patent

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Efficient refresh operation for semiconductor memory devices

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Efficient register for additive latency in DDR2 mode of...

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Efficient semiconductor burn-in circuit and method of operation

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Efficient sense command generation

Static information storage and retrieval – Read/write circuit – Particular read circuit
Reexamination Certificate

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Efficient word lines, bit line and precharge tracking in...

Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate

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