Efficient redundancy method for RAM circuit

Details Efficient redundancy method for RAM circuit Efficient redundancy method for RAM circuit

1991-05-30

1993-11-09

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Multiplexing

3652257, G11C 700

Patent

active

052609022

ABSTRACT:
A redundancy system for a random access memory circuit includes a plurality of groups, each having first and second multiplexers on opposite sides thereof, each group being made up of two squads each containing four columns. Pairs of columns from one group are interlaced with pairs of columns of the other group.

REFERENCES:
patent: 4601019 (1986-07-01), Shah et al.
Atsushi Ohba et al., "A 7-ns 1-Mb BiCMOS ECL SRAM with Shift Redundancy", IEEE Journal of Solid State Circuits, vol. 26, No. 24, Apr. 1991, pp. 507-511.

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