Efficient column redundancy techniques

Details Efficient column redundancy techniques Efficient column redundancy techniques

2005-03-01

2005-03-01

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189020, C365S230020

Reexamination Certificate

active

06862230

ABSTRACT:
The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.

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