Static information storage and retrieval – Read/write circuit – Erase
Patent
1988-05-11
1990-08-14
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Erase
365185, 365104, 357 235, 307465, G11C 1140
Patent
active
049493094
ABSTRACT:
An array of floating gate transistors is connected so that some of the floating gate transistors within the array can be erased without affecting the state of other floating gate transistors within the array, or in the alternative, the entire array of floating gate transistors can be erased simultaneously.
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Samachisa et al., "A 128K Flash EEPROM Using Double-Polysilicon Technology", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 676-683.
Mukherjee et al, "A single Transistor EEPROM Cell and Its Implementation in a 512K CMOS EEPROM", I.E.D.M., 1985, pp. 616-619.
Johnson et al., "A 16Kb Electrically Erasable Nonvolatile Memory", IEEE International Solid-State Circuits Conference, 1980, pp. 152-153.
Catalyst Semiconductor, Inc.
Garcia Alfonso
Hecker Stuart N.
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