Efficient implementation of a read scheme for multi-threaded...

Details Efficient implementation of a read scheme for multi-threaded... Efficient implementation of a read scheme for multi-threaded...

2007-04-10

2007-04-10

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S189030, C365S189050

Reexamination Certificate

active

11040058

ABSTRACT:
A multi-threaded memory system including a plurality of entries, each one of the plurality of entries including a plurality of threads, each one of the plurality of threads including an active cell and a shared read cell. The shared read cell has an output coupled to a read bit line and a corresponding plurality of inputs coupled to an output of the corresponding active cells in each one of the plurality of threads. A multi-threaded memory system is also described.

REFERENCES:
patent: 5602781 (1997-02-01), Isobe
patent: 5778243 (1998-07-01), Aipperspach et al.
patent: 6298431 (2001-10-01), Gottlieb
patent: 2003/0051123 (2003-03-01), Takamuki
patent: 0622732 (1994-11-01), None
patent: 2286265 (1995-08-01), None
patent: WO 01/53935 (2001-07-01), None
patent: WO 2005/022381 (2005-03-01), None
patent: WO 2005/022384 (2005-03-01), None
Combined Search and Examination Report Under Sections 17 and 18(3), Jan. 4, 2006 (6 pages).

Affiliated with

Also associated with

Rating

Efficient implementation of a read scheme for multi-threaded... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Efficient implementation of a read scheme for multi-threaded..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient implementation of a read scheme for multi-threaded... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3741913