Efficient sense command generation

Details Efficient sense command generation Efficient sense command generation

2008-04-23

2010-12-14

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S210100, C365S208000, C365S194000, C365S196000

Reexamination Certificate

active

07852688

ABSTRACT:
In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica circuit also including a comparator that asserts an output in response to comparing a voltage of the replica bit line to a threshold, the sense command being a buffered version of the output from the comparator.

REFERENCES:
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patent: 2004/0114424 (2004-06-01), Yoshida
patent: 2007/0171750 (2007-07-01), Oh
patent: 2008/0043555 (2008-02-01), Hold
patent: 2008/0084777 (2008-04-01), Montoye et al.
patent: 2008/0123387 (2008-05-01), Imai

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