Efficient read, write methods for multi-state memory

Details Efficient read, write methods for multi-state memory Efficient read, write methods for multi-state memory

2002-05-21

2004-06-15

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S051000, C365S185050

Reexamination Certificate

active

06751129

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to mass digital data storage systems. More particularly, the present invention relates to systems and methods for reducing the overhead associated with multi-state storage systems.
2. Description of the Related Art
The use of non-volatile memory systems such as flash memory storage systems is increasing due to the compact physical size of such memory systems, and the ability for non-volatile memory to be repetitively reprogrammed. The compact physical size of flash memory storage systems facilitates the use of such storage systems in devices that are becoming increasingly prevalent. Devices which use flash memory storage systems include, but are not limited to, digital cameras, digital camcorders, digital music players, handheld personal computers, and global positioning devices. The ability to repetitively reprogram non-volatile memory included in flash memory storage systems enables flash memory storage systems to be used and reused.
Data that are streamed into a memory system are generally written into memory cells or, more generally, storage elements on a bit-by-bit basis and read out of the storage elements on a bit-by-bit basis. As will be understood by those skilled in the art, write operations are generally slow, e.g., take a relatively long time to perform. Often, some read operations may be time-consuming as well.
As will be appreciated by those skilled in the art, bits that are to be written into or read out of cells are typically buffered. Bits are generally buffered when a data bus has a width to and from memory that is substantially less than the number of bits which may be written to, read from, or operated on in parallel in the memory. Buffering bits also alleviates bandwidth and power consumption issues.
A master-slave register bit is generally needed for each bit that is to be buffered. Typically, each master-slave register bit requires up to approximately twenty-four transistors for implementation. One conventional master-slave register, or master-slave flip flop, is shown in
FIG. 12. A
master-slave register
1200
which includes a reset function is suitable for use in buffering a bit. For a non-volatile memory system, as for example a memory system that includes up to approximately 4000 cells or storage elements that may be operated on simultaneously, one or two bits may generally be stored in each cell. As such, when each of the 16,000 bits are to be buffered, 16,000 master-slave register bits may be required, which, in turn, generally requires a relatively high number of total transistors. Implementing a relatively high number of transistors which support master-slave register bits may occupy more physical space within a memory system than desired and therefore be more expensive.
In order to reduce the number of transistors needed to buffer bits in a memory device, single data latches may be implemented for use as buffers in lieu of master-slave latches or master-slave register bits. Each memory cell may operated simultaneously have one or more associated latches which are suitable for buffering both data that are to be stored in the memory cell and data that are to be read from the memory cell. The use of single data latches rather than master-slave latches may allow the number of transistors associated with buffering capabilities to be reduced by up to approximately fifty percent. However, while master-slave latches use a relatively simple clocking scheme to select individual master-slave latches to be accessed, the use of data latches generally require more complicated addressing schemes to access individual data latches. Such addressing schemes may, in some cases, require more transistors than are required to support master-slave latches or master-slave bits.
Since an addressing scheme which may utilize a relatively high number of transistors may not be efficient, ripple clocks are sometimes implemented to enable data latches to be accessed sequentially. That is, the single data latch associated with each memory cell may be accessed sequentially with respect to the data latches associated with other memory cells in a memory device. One example of data latches which are accessed by a ripple clock is shown in
FIG. 13
a
. A system
1300
includes latches
1310
and master-slave registers or master-slave flip-flops
1314
. Latches
1310
are data latches which are each associated with a memory cell, and are enabled by latch enable (LE) signals. Specifically, latch
1310
a
is enabled by an LEA signal, latch
1310
b
is enabled by a LEB signal which is an output of flip-flop
1314
, and latch
1310
c
is enabled by a LEC signal which is an output of flip-flip
1314
b
. Flip-flops
1314
are generally controlled by a common clock (CK) signal.
In general, only one LE signal is asserted at any given time, and the asserted LE signal is effectively propagated by flip-flops
1314
. The set of asserted LE signals effectively forms a ripple clock. As shown in a timing diagram
1350
of
FIG. 13
b,
an LEA signal
1360
a,
an LEB signal
1360
b
, and an LEC signal
1360
c
are such that only one LE signal
1360
is asserted, e.g., at a high value, at any point in time to trigger latches
1310
of
FIG. 13
a.
A ripple clock that is implemented in a system such as system
1300
of
FIG. 13
a
requires a master-slave latch or a flip-flop which generates the enable signal or signals for each set of latches to be accessed serially. As such, the use of ripple clocks and a single data latch for each memory cell may not reduce the number of transistors needed in an overall memory device.
Therefore, what is needed is a system and a method which enables bits to be written efficiently into and read efficiently from memory cells without requiring a relatively high number of components such as transistors. That is, what is desired is a system and a method for reducing the overhead associated with writing bits into and reading bits from a multi-state memory cell while enabling the writing and the reading to occur efficiently.
SUMMARY OF THE INVENTION
The present invention relates to a system and a method for efficiently writing data to and reading data from memory cells. According to one aspect of the present invention, a memory system includes a first storage element, a data source, a first element, a second element, and a ripple clock. The data source provides a plurality of bits to be stored in the first storage element, and the first element receives a first bit from the data source, and also clocks the first bit into the second element The first element then receives a second bit of the plurality of bits from the data source substantially while the first bit is being stored into the first storage element. The ripple clock enables access to the first element and the second element such that the first bit and the second bit may be pipelined.
In one embodiment, the ripple clock also allows substantially concurrent access to the first storage element and at least a second storage element included in the plurality of storage elements. In another embodiment, the first buffering element is a first latch and the second buffering element is a second latch.
The use of a plurality of buffering elements such as latches to pipeline data bits either into or out of a multi-state memory cell allows write and read operations, respectively, to occur more efficiently. As such, the overhead cost of multi-state storage may be reduced. By loading a bit into a second latch associated with a group of memory cells while a bit is being written from a first latch into the memory cell, the time associated with loading the bit into the second latch may effectively be masked. Hence, an overall write process may occur more efficiently.
According to another aspect of the present invention, a computing system includes a host that provides a first bit and a second bit, and a storage device that is in communication with the host. The storage device includes a first storage element which clocks the first bit into a

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