Efficient back bias (V.sub.BB) detection and control scheme for

Details Efficient back bias (V.sub.BB) detection and control scheme for Efficient back bias (V.sub.BB) detection and control scheme for

1997-12-18

2000-09-05

Phan, Trong

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36523008, G11C 700

Patent

active

061152951

ABSTRACT:
An efficient back bias (V.sub.BB) detection and control circuit make possible a low voltage memory device and includes an on-chip V.sub.BB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (-(.vertline.2 VTP.vertline.+VTN)) during power-up and a second voltage level (-.vertline.2 VTP.vertline. during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.

REFERENCES:
patent: 4581718 (1986-04-01), Oishi
patent: 5065091 (1991-11-01), Tobita
patent: 5315557 (1994-05-01), Kim et al.
patent: 5721510 (1998-02-01), Miyajima

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