Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2007-07-31
2007-07-31
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S233100, C365S189050, C365S230080
Reexamination Certificate
active
11071852
ABSTRACT:
An additive latency circuit for a DDR2 standard compliant integrated circuit memory includes a half flip-flop register assigned for each case of additive latency. A unique clock is generated to control each bit in the register chain. Sufficient register bits are required in the chain to support the highest additive latency specified. For latency settings less than the maximum, those clocks assigned to the bits above the chosen latency are enabled so the data passes through un-clocked. For the additive latency zero case, a separate bypass path is provided. Both address and command information is delayed by the additive latency delay chain. Once delayed by the proper number of cycles, the address information remains in that state until the time when a new state is required. Command information remains valid for one cycle upon reaching the proper delay point. A reset circuit is provided to reset command signals.
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Barnett Craig
Faue Jon Allan
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
ProMOS Technologies Inc.
Weinberg Michael
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