Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1999-11-10
2001-03-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S185250
Reexamination Certificate
active
06205061
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to integrated circuits systems that include integrated circuits and, more particularly, to memory circuits such as dynamic random access memory (DRAM) circuits and, even more particularly, to back bias (V
BB
) detection and control schemes for low voltage DRAM circuits.
BACKGROUND OF THE INVENTION
Achieving proper operation of a memory circuit, such as a DRAM, typically requires an initial pause of 200 &mgr;sec followed by a minimum of eight initialization cycles after reaching the full V
CC
level. Within the generally specified power-up pause of 200 &mgr;sec, reliable DRAM operation demands on-chip generated back bias voltage (V
BB
). Providing the needed V
BB
reduces junction capacitance, reduces substrate leakage and prevents forward biasing of junctions. Generating a deep V
BB
level within the specified power-up, however, becomes difficult at low operating voltages (e.g., approximately 3.3 V). This is particularly true if the V
BB
load capacitance is high, such as is the case for sub-micron technologies and higher DRAM densities. For instance, the typical V
BB
load capacitance of a 16 Mb DRAM employing trench capacitor cells as storage elements is about 240 nf.
One type of circuit design for initializing and enabling peripheral circuits on a memory chip generates internally a positive pulse RID(RAS_ Input Disable). In this circuit, RID is designed to go positive as soon as power-on conditions are detected and reset when V
BB
reaches a preset level. The resetting is usually accomplished by means of an analog sensor, which detects when the V
BB
level is 2Vtn below ground. For example, TABLE 1 documents RID trip points for the 16 Mb shrink (16 MS) low voltage (3.3 V) DRAM fabricated using 0.5 &mgr;m technology. As TABLE 1 shows, RID reset is marginal to the power-up specification of 200 &mgr;s at 2.6 V, 100° C. and using a MSIG (minus sigma) process model.
TABLE 1
16 MS SIMULATION RESULTS
SIMULATION
CONDITIONS/MODEL
RID TRIP POINT
VBB @ RID
2.6 V, 100 C.|MSIG
203 us
−0.89 V
4.0 V, −10 C.|PSIG
45 us
−1.12 V
Of particular importance is the fact that if RID is not reset within the power-up spec time, then the device operation cannot be guaranteed.
In other words, this method uses RID to manipulate V
BB
pumping during power-up in the memory device. RID is made a function of V
BB
, through a predetermined level sensor. V
BB
pumping starts as soon as power-on is detected and stops after RID is reset. Such a scheme may be inadequate for low voltage operations, because at 16 MB densities, higher substrate capacitances result. Thus, V
BB
may not reach a deep enough level to reset RID. This will keep the device in initialization mode, and prohibit normal memory device operation.
One method to reset RID expeditiously is to pump harder the V
BB
, so that RID reset is not marginal to spec. Usually, V
BB
pumping during power-up is stopped after RID is reset. This method extends pumping beyond RID reset so that the V
BB
level is deep on power-up. As the process models/operating conditions change, if pumping is extended uncontrolled, V
BB
becomes too deep and may adversely affect memory device operation.
SUMMARY OF THE INVENTION
In light of the above limitations, there is a need for an improved memory device initialization circuit that avoids the limitations by providing a sufficiently deep and prompt back bias supply for a memory device during power-up, but which back bias supply is not too deep for normal low voltage operation.
The present invention, therefore, provides a back bias control circuit for a memory device, such as a DRAM, that eliminates or substantially reduces the slow and low voltage power-up problems affecting known back bias supply circuits.
According to one aspect of the invention, there is provided an efficient back bias (V
BB
) detection and control circuit that makes possible a low voltage memory device and thus includes an on-chip V
BB
level sensor having a dynamic voltage reference shift circuit for establishing a first voltage level during power-up and a second voltage level during normal operation. The first voltage is of a deeper level to achieve a short power-up interval. The second voltage level is of a level less deep than the first voltage for achieving low power operation.
According to another aspect of the invention, there is provided an on-chip V
BB
level sensor that chooses a −(|2VTP|+VTN) reference during power-up and a −(|2VTP|) reference after power-up. A power-up complete signal is combined with the sensor output to conditionally bypass the extra N-channel transistor in the sensor circuit, thus changing the sensing level from −(|2VTP|+VTN) to −(|2VTP|) dynamically. The sensor output is used to keep the pumps, including a booster pump, a high power pump, and a low power pump, for example, enabled until a deep V
BB
condition is detected. This quickens the substrate pumping enabling us to achieve deeper V
BB
level in a shorter time interval. The feedback path ensures that until the power-up condition is reached, −(|2VTP|+VTN) sensing is enabled. The on-chip V
BB
detection and control circuit cuts off all extra pumping once deep V
BB
is sensed by the sensor. Once the memory device reaches the powered-up condition, the present invention enables the feedback path to N-channel transistor. This results in bypassing the N-channel transistor. From this point onward, only the −(|2VTP|) reference level appears in the sensor input path.
A technical advantage of the present invention is its use of an on-chip oscillator that helps low power operation. The on-chip oscillator makes use of the dynamically reconfigured −(2VTP) level sensor (described above), during normal operation.
A technical advantage of the present invention is that it provides for RID resetting at a relatively shallow V
BB
level. The present invention, therefore, allows the device to initialize within the specified time for the DRAM and pumps are not cut off. This allows V
BB
to reach a deep level.
Other technical advantages that the present invention provides is achieving desired (deep) V
BB
level with shorter power-up interval, and reconfiguring of the same sensor for low power operation once the sensor circuit detects the powered-up condition.
REFERENCES:
patent: 5642313 (1997-06-01), Ferris
Rao Sadashiva
Surlekar Vipul
Brady W. James
Cimino Frank D.
Nelms David
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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